Computer Organisation and Architecture | COA | MCQ

Chapter 2:
Multiple Choice Questions:
1. What number system was used in the ENIAC machine?
A. Binary B. Decimal
C. Octal D. Hexadecimal
ANS: B
2. The Memory Address register stores the address of the word stored in which part of
the architecture?
A. I/O B. Program Counter
C. Memory Buffer Register D. None of the above
ANS: C
3. Which part of the EDVAC architecture temporarily holds instructions?
A. Program Counter B. Instruction Register
C. ALU Unit D. Instruction Buffer Register
ANS: D
4. The five important parts of the Von Neumann Machine are:
A. Fetch Unit, ALU, Memory, Registers and I/O
B. Central Arithmetic, Central Control, Memory, Registers and I/O
C. Fetch Unit, Decode, ALU, Memory and I/O
D. Central Arithmetic, Fetch Unit, Control, Registers and Buses.
ANS: B
5. When is the execute cycle performed?
A. When instruction is fetched
B. After registers are decoded
C. When the opcode is in the Instruction register
D. When the instruction is buffered in the buffer register.
ANS: C
6. What is the second generation computers made?
A. Vacuum tubes
B. Integrated Circuits
C. Resistors
D. Transistors
ANS: D
7. What are the fundamental blocks of the third generation computers and what were
they made of?
A. Integrated Circuits consisting of capacitors
B. Digital Circuits using vacuum tubes
C. Integrated Circuits made using transistors
D. None of the above
ANS: C
8. What did Moore’s law predict about the density and size of future generation chips?
A. Density decreases and size doubles
B. Density increases drastically and size reduces
C. Density increases but size remains the same
D. No impact on size and density
ANS: B
9. What technology was used to create memories?
A. Vacuum tube based technology
B. Same integrated circuit technology as the processors
C. Capacitor based network technology
D. Inductive circuitry
ANS: B
10. Instructions can be speculatively executed using what two important steps?
A. Instruction fetching & decode
B. Speculative fetch and Branch prediction
C. Branch prediction and data analysis
D. None of the above
ANS: C
11. What changes can be done to the I/O buses to speedup the transfer of data
between the processor and memory
A. Increase bus width
B. Decrease the frequency of transfer
C. Add buffers for the I/O
D. All of the above
ANS: D
12. Advances in integrated circuit technology can lead to the following detractors
A. Decrease in speed/ performance
B. Increase in power consumption and dissipation
C. All the above
D. None of the above
ANS: B
13. The Intel MMX technology was introduced with which core?
A. Pentium Pro B. 80286
C. Pentium III D. Pentium II
ANS: D
14. Which of the following depicts and Embedded system
A. Multi-core processor unit.
B. Application specific Core
C. Hardware Software Combination to perform specific application
D. All of the above
ANS: C
15. The performance of a processor can be measured using
A. Clock period
B. Cycles per Instruction
C. Throughput
D. All of the above
ANS: D
16. The speedup of a processor is estimated using which of the following parameters
A. Throughput
B. Execution time in one and N processors
C. Cycles per instruction in one and N processors
D. None of the above
ANS: B
Chapter 3:
Multiple Choice Questions:
1. How are data and instructions stored in the Von Neumann architecture?
A. In separate memories B. Dual ported memory
C. Unified read-write memory D. None of the above
ANS: C
2. What are the parts of an instruction cycle ?
A. Fetch and Execute Cycle B. Fetch, decode and execute cycles
C. Decode and Store cycle D. Fetch, decode, execute and store.
ANS: A
3. Where is the fetched instruction stored?
A. Instruction register B. Program Counter
C. Instruction buffer register D. None of the above
ANS: A
4. The only data register in the processor is
A. Store register B. Data Buffer register
C. Accumulator D. Value register
ANS: C
5. What are the register(s) involved in reading & writing data/instruction to the memory?
A. Memory address and memory buffer register
B. Store register
C. Program counter
D. Write back and Instruction register
ANS: A
6. Which of the following is not a state of the instruction cycle?
A. Operand address calculation
B. Data write back
C. Instruction fetch
D. None of the above.
ANS: B
7. Which of the following is a type of interrupt?
A. I/O interrupt B. Program Interrupt
C. Hardware/power failure D. All of the above
ANS: D
8. Which of the following approach is used to handle multiple interrupts?
A. Parallel interrupt processing
B. Disable interrupts and priority assignment
C. Interrupt wait
D. None of the above.
ANS: B
9. What are the interconnection wires not in the bus structure?
A. Data lines B. Instruction lines
C. Address lines D. Control lines
ANS: B
10. List a few pins that are not in the memory, but present in the I/O module
A. Control signals B. Interrupt Signals
C. External data D. B & C above
ANS: D
11. To which of the following buses is the memory connected to?
A. High-performance bus B. Control bus
C. System Bus D. Interface bus
ANS: C
12. The local bus connects which two components of the system?
A. Memory and I/O module
B. Processor and cache
C. Cache and Register bank
D. None of the above
ANS: B
13. What signals are used to validate data and instructions?
A. Timing signals B. Control signals
C. Acknowledgement signals D. Interrupt signals
ANS: A
14. In which type of timing does the clock act as a reference?
A. Interrupt timing B. Asynchronous timing
C. Synchronous timing D. Sequential timing
ANS: C
15. Which of the following is not a PCI bus functional group?
A. Error correcting pins B. System pins
C. Arbitration pins D. Interface control pins
ANS: A
16. Which of the following is a bus arbitration scheme?
A. Round-robin B. Priority
C. First come first serve D. All of the above.
ANS: D
Chapter 4:
Multiple Choice Questions:
1. How are data stored in the internal memory?
A. Bytes B. Words
C. Pages D. A or B
ANS: D
2. Which among the following is not as method of accessing data?
A. Sequential B. Asynchronous
C. Random D. None of the above
ANS: B
3. The unit of transfer between the levels of memory is defined by
A. Type of memory access B. Number of electrical lines in
and out of memory
C. Distance between the memory and processor D. All of the above
ANS: B
4. Performance of the memory is decided by which of the following parameters
A. Transfer rate B. Latency
C. Cycle time D. All of the above
ANS: D
5. Which of the following memory types is visible to the user?
A. Main memory B. Virtual Memory
C. Level 3 cache D. None of the above
ANS: A
6. Which of the following is not included in each line of the cache
A. Tag B. Valid bit
C. Flag D. Dirty bit
ANS: C
7. Victim caching helps what type of cache architecture?
A. Fully-associative B. Direct mapped
C. Set-Associative D. None of the above
ANS: B
8. Memory address in set-associative cache is interpreted into the three fields namely;
A. tag, set and word B. tag, set and byte
C. valid bits, set and byte D. valid bits, set and word
ANS: A
9. Random cache line replacement policy performs close to which other policy
A. LRU B. LFU
C. FIFO D. All of the above
ANS: D
10. When is a cache block is written into the main memory
A. Valid bit is not set B. Every cycle
C. Dirty bit is set D. None of the above
ANS: C
11. Split caches indicate separate
A. L1 and L2 cache B. L2 and L3 cache
C. Data and Instruction cache D. None of the above
ANS: C
12. Where is each cache in the hierarchy in the processor
A. On-chip L1 and Off-chip L2,L3 B. Off-chip L1,L2 and L3
C. On-chip L1,L2 and L3 D. On-chip L1,L2 and Off-chip L3
ANS: C
13. The logical cache in the hierarchy is accessed using
A. Decimal numbers B. Physical Address
C. Virtual address D. None of the above
ANS: C
14. Prefetching can be done only in what type of cache
A. Fully-associative B. Direct mapped
C. Unified cache D. Split-cache
ANS: D
16. As you go down the hierarchy,
A. Latency increases B. Cost per bit reduces
C. Capacity increases D. All of the above
ANS: D
Chapter 5:
Multiple Choice Questions:
1. An important attribute of RAM memories is
A. Random access & non-volatile B. Volatile
C. Sequential access D. None of the above
ANS: B
2. Which of the following is a type of DRAM
A. Advanced DRAM B. DDR DRAM
C. RDR DRAM D. None of the above
ANS: D
3. Important difference between SRAM and DRAM
A. Static/Dyn & no refresh for SRAM B. Static/Dyn & no refresh for DRAM
C. no refresh for DRAM D. None of the above
ANS: A
4. In a DRAM, depending on what is the cell value decided as 1 or 0.
A. Max capacitor charge B. Transistor threshold voltage
C. DC voltage high D. Input voltage
ANS: B
5. Why does DRAM support more memory cells in a given area than SRAM
A. DRAM has smaller cell B. SRAM has large cell area
C. DRAM is more dense D. All of the above
ANS: D
6. How long does a static SRM holds data
A. Eternally B. Until power is supplied
C. Only during manufacturing D. None of the above
ANS: B
7. How often/how is data written into the ROM
A. Anytime/when required B. Before use – by microprogramming
C. During manufacturing D. All of the above
ANS: C
8. What happens when a bit of data is incorrect in a ROM
A. Error correction will be used B. Redundancy will help
C. ROM cannot be used D. None of the above
ANS: C
9. From the following, which type of memory is not a read-mostly memory?
A. EEPROM B. PROM
C. Flash D. EPROM
ANS: B
10. In a DRAM, refresh circuitry is added to help which unit?
A. Data buffer B. Refresh counter
C. Timing and control D. Column decoder
ANS: D
11. The most common pins on a memory chip package are:
A. Vcc and Vss B. Write and read enable
C. Chip enable (CE) & Vpp D. All of the above
ANS: A
12. When consecutive memory locations are stored in difference memory banks, it leads
to
A. Speedup – parallel access B. Increased latency
C. Does not help/degrade D. None of the above
ANS: A
13. What signals provide timing to the chip
A. RAS and WE B. RAS and CAS
C. Clock and WE D. All of the above
ANS: B
14. Cause of hard failures are:
A. Manufacturing defects B. Radiation
C. Environmental protection D. All of the above
ANS: A
15. If one bit of the syndrome is set to 1, it means
A. Rewrite the entire word B. Correction is required
C. Bit inversion is required D. None of the above
ANS: D
16. What is the difference between SEC and SEC-DED in terms of the bits used?
A. SEC-DEC uses 1 extra bit B. SEC uses two extra bits
C. SEC-DEC uses 1 bit less D. None of the above
ANS: A
Chapter 6:
Multiple Choice Questions:
1. Redundancy is a built-in feature here
A. Magnetic disks B. RAID
C. Serial I/O tapes D. Optical disks
ANS: B
2. The megnetoresistive sensor (MR) increases what capability in newer rigid disks?
A. Operating frequency B. Area
C. Access times D. None of the above
ANS: A
3. Each sector in the disk can be reached at the same time using this layout
A. Multiple zone layout B. Constant velocity layout
C. Static sector layout D. None of the above
ANS: B
4. Data access time depends on
A. Seek time B. Operating frequency
C. Rotational delay D. All of the above
ANS: D
5. In RAID architecture, data is distributed as an array by a scheme called
A. Interleaving B. Stripping
C. De-centralizing C. None of the above
ANS: B
6. RAID level 0 is primarily used in applications where
A. Cost is a priority B. Reliability is a priority
C. Area is a priority C. All of the above
ANS: A
7. The chief difference between RAID 4 and RAID 5 lie with
A. Parity strips B. Redundant disks
C. Performance D. All of the above
ANS: A
8. Typical technique used to write/read data onto magnetic tapes is
A. Compound parallel recording B. Serpentine recording
C. Multiple access recording D. None of the above
ANS: B
9. Bit density is more in which device
A. Compact disk B. Magnetic tape
C. DVD D. Magnetic disk
ANS: C
10. Change of phase in phased disks is performed by
A. Optical light B. Laser
C. Magnetization D. None of the above
ANS: B
11. The primary advantage of RAID level 6 is
A. High data availability B. High data accessibility
C. Low data loss D. All the above
ANS: A
12. Data in CDROM are arranged in blocks with what of the following fields?
A. Data B. Auxiliary
C. Header D. All the above
ANS: D
13. What property of the CDROM is similar to magnetic disks
A. Constant linear velocity B. Access rate
C. Parallel access frequency D. None of the above
ANS: A
14. What property makes the CDROM be used for archival storage.
A. Redundancy B. Rewritable
C. Removable D. All the above
ANS: C
15. Which of the following is not a head mechanism
A. Aerodynamic gap B. Intrasector gap
C. Fixed gap D. Contact
ANS: B
16. Which of the following substrates for magnetic disks has better capacity to withstand
shock and damage
A. Resin B. Poly-crystalline
C. Glass D. Quartz
ANS: C
Chapter 7:
Multiple Choice Questions:
1. Interfaces to memory and I/O devices are made through
A. Central Switch B. Buses
C. Data links D. All of the above
ANS : D
2. What converts data from electrical to other forms of energy in an I/O module?
A. Convertor B. Transformer
C. Transducer D. Arbiter
ANS : C
3. Which of the following is a example for a communication I/O?
A. Monitor B. Mouse
C. Modem D. USB
ANS : C
4. Processor communication does not involve
A. Command decoding B. Status reporting
C. Error correcting D. None of the above
ANS : C
5. I/O command type
A. Read B. Control
C. Test D. All the above
ANS : D
6. This technique for data transfer does not involve the processor
A. Direct Memory access B. Programmed I/O
C. Memory-mapped I/O D. All the above
ANS : A
7. Which one of the following performs arbitration
A. Intel 8237A B. Intel 82C55A
C. Intel 82C59A D. Intel 80386
ANS : C
8. In an Interrupt -driven I/O, when an interrupt is detected, details on the current
processor condition is stored in
A. Return address register B. Program counter
C. Program status word D. Memory bank
ANS : C
9. The address of I/O device is communicated using
A. Data buses B. Data Lines
C. Address bus D. Status lines
ANS : B
10. This register can be used to mask the channels of DMA using one write operation
A. Single Mask B. Status
C. Command C. None of the above
ANS : C
11. Communication control using terminal can be done with
A. DMA B. Complete processor control over I/O
C. I/O with local memory and control D. All of the above
ANS : C
12. This type of I/O channel can transfer high-speed data with only one device at a time
A. Control channel B. Selector channel
C. Sequential channel D. Multiplexor channel
ANS : B
13. A Parallel interface is used for connection between high-speed devices such as
A. Terminal B. Keyboard
C. Tape D. None of the above
ANS : C
14. Example(s) of multi-point configuration based communications can be devices such
as
A. Monitor B. Keyboard
C. External modem D. None of the above
ANS : D
15. This layer of the FireWire bus controls the data transmission using priority and
fairness protocols
A. Link layer B. Isochronous layer
C. Transaction layer D. None of the above
ANS : D
16. What performs the functions of point-to-point connections between servers
A. Link layer B. Infiniband switch
C. Target channel adapter D. Subnet
ANS : B
Chapter 10:
Multiple Choice Questions:
1. After reading the Opcode, the source and destination operand data are stored in
A. ALU itself B. Registers
C. Counters D. None of the above
ANS : B
2. Symbolic representation of instructions use which type of addressing mode?
A. Register addressing B. Memory addressing
C. Immediate addressing D. All of the above
ANS : D
3. Address of the next instruction can be obtained from
A. Opcode B. Program counter
C. Instruction queue D. Any of the above
ANS : B
4. What is the maximum number of addresses that an instruction (opcode) can contain?
A. Eight B. Six
C. Four D. Two
ANS : B
5. This code can be used to characters
A. Morse code B. Hexadecimal code
C. Binary code D. ASCII code
ANS : D
6. Data transfer type instruction can involve
A. Data to & from memory B. Data between registers
C. Data between I/O D. All of the above
ANS : D
7. This block is always used between instructions
A. ALU B. Register
C. Memory D. None of the above
ANS : B
8. Logical shifts are used for
A. Obtain next instruction address B. Shift address bits
C. Perform arithmetic operation D. Isolating fields within a data word
ANS : D
9. These operation may involve the DMA controller
A. Arithmetic instructions B. I/O Instructions
C. Logical instructions D. None of the above
ANS : B
10. Only instructions with special permission are allowed to change the contents of
A. Memory B. Instruction registers
C. Control registers D. All of the above
ANS : C
11. Branches and jumps are types of
A. Arithmetic instructions B. Data or Logical instructions
C. I/O instructions D. Transfer of control instructions
ANS : D
12. Modularity helps in
A. Exceptions B. Data transfer
C. Procedure calls D. None of the above
ANS : C
13. Return addresses can be stored in
A. Top of the stack B. Return address register
C. Procedure call D. All of the above
ANS : A
14. Stack frames are primarily used in
A. Logical instructions B. Arithmetic instructions
C. Call/Return instructions D. None of the above
ANS : C
15. SIMD instructions are typically used in
A. Arithmetic operations B. MMX – graphics and math operations
C. Signal processing D. All of the above
ANS : B
16. Memory management operations are performed by
A. User B. Programmer
C. Operating system D. Hardware
ANS : C
Chapter 11:
Multiple Choice Questions:
1. While deciding the proper addressing mode, the trade-off is between operand
address range and
A. ALU size B. Number Registers
C. Flexibility D. None of the above
ANS : C
2. The ALU or shifter is used to find the exact location of one of the operands in
A. Immediate addressing B. Register Indirect addressing
C. Displacement addressing D. None of the above
ANS : C
3. The main advantages of register addressing mode are
A. Flexibility and Speed B. Speed and number of address bits
C. Address bits D. All of the above
ANS : D
4. This concept is used while implementing instructions in relative addressing mode
A. Register reuse B. Temporal locality
C. Spatial locality D. None of the above
ANS : C
5. What type of programs can be implemented using indexing addressing mode?
A. Recursive B. Convolution
C. All of the above D. Loops
ANS : C
6. Post and pre-indexing are done for instructions of indexing and what other
addressing mode?
A. Immediate B. Register
C. Displacement D. Indirect
ANS : D
7. Transfer-of-control type instructions typically use what type of addressing mode?
A. Immediate B. Register indirect
C. Relative D. None of the above
ANS : A
8. Load/store type instruction use
A. Indirect B. Immediate
C. Relative D. All of the above
ANS : A
9. The instruction length has to be a multiple of
A. Integer array B. Character length
C. Page size D. None of the above
ANS : B
10. x86 instructions have a prefix to indicate control over shared memory
A. Load prefix B. Lock prefix
C. Dirty data prefix D. Coherency prefix
ANS : B
11. The PDP-8 microinstructions are used for
A. Immediate addressing B. Register reference addressing
C. Memory reference D. None of the above
ANS : B
12. Direct addressing is used in
A. Memory referencing B. PDP-8
C. PDP-10 D. PDP-11
ANS : C
13. This instruction format does not have a fixed instruction length
A. VAX B. PDP -10
C. PDP-11 D. PDP-8
ANS : C
14. In the VAX instruction format, the opcode is of
A. 8 bytes B. 2 bytes
C. 1 byte D. None of the above
ANS : B
15. ARM instruction have an opcode length of
A. 8 bytes B. 0.5 bytes
C. 1 byte D. None of the above
ANS : A
16. How is the decision to use thumb or 32 bit instruction decided in an ARM core?
A. Program counter B. Return address register
C. Processor control register D. All of the above
ANS : A